This application relates generally to integrated circuit chip carrier designs and specifically to leaded ceramic chip carriers fabricated utilizing the direct bond process for securing a copper lead frame to a ceramic substrate.
Integrated circuits are produced in the form of flat, generally rectangular chips which have terminal areas or terminal pads usually located along the side edges of the chip. In order to assemble such an integrated circuit chip into a complex circuit assembly the chip is usually mounted or packaged in a chip carrier. Chip carriers are designed to provide electrically conductive paths from the chip terminals to the edge of the chip carrier package (or beyond) so that the chip can be connected to further circuitry external to the carrier.
To accomplish the above requirements, chip carriers usually provide a lead frame comprising a plurality of leads supported on an insulating substrate or in a housing. The leads are provided with first regions proximate the chip terminals, which are adapted for electrical coupling (either directly or through an intermediate conductor) to the chip terminals to thereby complete an electrical connection between the lead frame and the chip terminals. The leads of the lead frame are also provided with second regions usually proximate an edge of the insulating substrate or housing, which are adapted for electrical coupling (either directly or indirectly) to electrical circuitry external to the carrier. This latter connection is accomplished in leadless chip carrier designs by means of terminals fixedly carried by the chip carrier body. Alternatively, in leaded carrier designs, these latter connections are accomplished by means of bridging conductors or leads which electrically interconnect the second regions of the lead frame leads to external circuits. In the case where the chip package is mounted on a printed circuit board, these external circuits consist of conductive runs on the surface of a printed circuit board.
A currently popular arrangement used to assemble chips into complex circuit assemblies is the leadless ceramic chip carrier in which fixed terminals on the ceramic carrier body are mounted or soldered directly to printed circuit runs on the surface of a printed circuit board. Such an arrangement is favored when it is necessary to meet the requirements of a demanding environment. In particular, such ceramic carrier arrangements are typically used or specified for military applications and for use in industrial computer and telecommunication applications, particularly where hermeticity is desired. Additionally, where high density surface mounting is mandatory chip carriers of the hermetically sealed leadless type are most frequently used. However, such arrangements cause undue stress on solder joints which interface the terminals of the chip carrier with the conductive runs on the printed circuit board. These stresses arise because of the large thermal mismatch between the chip carrier's alumina body (with a thermal coefficient of expansion of approximately 6 ppm/.degree.C.) and printed circuit board materials of various kinds with type thermal coefficients of expansion in the approximate range of 20 to 30 ppm/.degree.C.). These differences in the coefficients of thermal expansion of the ceramic carrier and underlying printed circuit board materials result in stresses at the electrical connections between the terminals on the body of the ceramic carrier and the conductive runs on the p.c. board surface which supports the package, and elsewhere in the assembly.
One general solution to the above discussed problem is to provide a board material that will nearly match the thermal coefficient of expansion of the alumina carrier. The military has concentrated its efforts on this method, i.e., a construction which approximately matches the ceramic's thermal coefficient of expansion to that of the underlying structure. A popular method to accomplish this is to use sandwiched layers of either copper-Kevlar-copper, copper-molybdenum-copper, or epoxy-graphite as the inner core of the multilayer structure. This diminishes the problem of thermal expansion mismatch since the inner core's thermal characteristics dominate the composite thermal coefficient of expansion and match that of the carrier's ceramic. Another variation is to use rigid composites, such as polyimide reinforced Kevlar or quartz, to achieve the low thermal coefficient of expansion required. These materials have sufficiently low thermal coefficients of expansion to keep shear strains of the solder joint to a minimum. However, routing and drilling of quartz in Kevlar fabric-reinforced composites are extremely difficult. In addition, microcracking of the brittle polyimide matrix resulting from excessive radial expansion of Kevlar fibers has stalled the widespread acceptance of polyimide Kevlar. The above methods, while promising, are expensive to implement.
A second general solution to the thermal mismatch problem is to provide compliant leads on the ceramic carrier, but the current methods of doing this add significant complexity and expense to an already costly unit because they use a variety of soldering, brazing, welding or thick film application steps.
With the use of compliant leads, the strain resulting from differing rates of thermal expansion between the ceramic substrate and the printed circuit board is dissipated by small and free movements of the leads which provide not only electrical connection to the conductive runs on the p.c. board, but also mechanical support for the chip package.
This application is directed to an improved chip carrier construction and method which overcomes the disadvantages of the prior art techniques for providing leaded ceramic chip carriers.